Commit 47f70a8e authored by BO ZHANG's avatar BO ZHANG 🏀
Browse files

tweaks

parent 3ab5bd4a
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+6 −4
Original line number Diff line number Diff line
@@ -28,12 +28,14 @@ class BaseDAG(ABC):
        self.dag_id = dag_id
        assert dag_id in DAG_LIST, f"{dag_id} not in DAG_LIST"

        with open(f"{dag_id}.yml", "r") as f:
            self.dag = yaml.safe_load(f)
        yml_path = os.path.join(DAG_CONFIG_DIR, f"{dag_id}.yml")
        json_path = os.path.join(DAG_CONFIG_DIR, f"{dag_id}.json")
        with open(yml_path, "r") as f:
            self.dag = yaml.safe_load(f)[0]
        assert (
            self.dag["dag_id"] == self.dag_id
        ), f"{dag_id} not consistent with definition in .yml file."
        with open(f"{dag_id}.json", "r") as f:
        ), f"{self.dag}"  # , f"{dag_id} not consistent with definition in .yml file."
        with open(json_path, "r") as f:
            self.msg_template = json.load(f)
        self.msg_keys = set(self.msg_template.keys())

+2 −0
Original line number Diff line number Diff line
@@ -42,6 +42,8 @@ MSC_SLS_CHIPID = [


class CsstMscL1Mbi(BaseDAG):
    def __init__(self):
        super().__init__("csst-msc-l1-mbi")

    def schedule(
        self,