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csst-sims
csst_msc_sim
Commits
07307ec4
Commit
07307ec4
authored
Jun 15, 2025
by
Fang Yuedong
Browse files
add default value (5e-5) of chip.badfraction
parent
9e56ecb1
Pipeline
#8744
passed with stage
in 0 seconds
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observation_sim/instruments/chip/Chip.py
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07307ec4
...
...
@@ -123,6 +123,7 @@ class Chip(FocalPlane):
self
.
dark_noise
=
0.02
# e/pix/s
self
.
rotate_angle
=
0.
self
.
overscan
=
1000
self
.
badfraction
=
5e-5
# Override default values
# for key in ["gain", "bias_level, dark_exptime", "flat_exptime", "readout_time", "full_well", "read_noise", "dark_noise", "overscan"]:
# if key in config["ins_effects"]:
...
...
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