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csst-sims
csst_msc_sim
Commits
2eb4e6b5
Commit
2eb4e6b5
authored
Oct 28, 2024
by
Wei Chengliang
Browse files
update codestyle-PEP8
parent
1a887d44
Pipeline
#7144
passed with stage
in 0 seconds
Changes
1
Pipelines
2
Show whitespace changes
Inline
Side-by-side
tests/test_crosstalk.py
View file @
2eb4e6b5
...
@@ -64,7 +64,7 @@ class detModule_coverage(unittest.TestCase):
...
@@ -64,7 +64,7 @@ class detModule_coverage(unittest.TestCase):
def
test_add_crosstalk
(
self
):
def
test_add_crosstalk
(
self
):
nsecy
=
2
nsecy
=
2
nsecx
=
8
nsecx
=
8
ny
,
nx
=
1024
,
1024
ny
,
nx
=
1024
,
1024
dy
=
int
(
ny
/
nsecy
)
dy
=
int
(
ny
/
nsecy
)
dx
=
int
(
nx
/
nsecx
)
dx
=
int
(
nx
/
nsecx
)
mapclip
=
np
.
zeros
([
dy
,
int
(
nsecx
*
nsecy
*
dx
)])
mapclip
=
np
.
zeros
([
dy
,
int
(
nsecx
*
nsecy
*
dx
)])
...
@@ -74,7 +74,7 @@ class detModule_coverage(unittest.TestCase):
...
@@ -74,7 +74,7 @@ class detModule_coverage(unittest.TestCase):
nsecy
=
1
nsecy
=
1
nsecx
=
16
nsecx
=
16
ny
,
nx
=
mapclip
.
array
.
shape
ny
,
nx
=
mapclip
.
array
.
shape
dy
=
int
(
ny
/
nsecy
)
dy
=
int
(
ny
/
nsecy
)
dx
=
int
(
nx
/
nsecx
)
dx
=
int
(
nx
/
nsecx
)
for
i
in
range
(
int
(
nsecy
*
nsecx
)):
for
i
in
range
(
int
(
nsecy
*
nsecx
)):
...
@@ -85,7 +85,7 @@ class detModule_coverage(unittest.TestCase):
...
@@ -85,7 +85,7 @@ class detModule_coverage(unittest.TestCase):
tmap
=
chip_utils
.
formatRevert
(
mapclip
,
nsecy
=
1
,
nsecx
=
16
)
# 1*16 -> 2*8
tmap
=
chip_utils
.
formatRevert
(
mapclip
,
nsecy
=
1
,
nsecx
=
16
)
# 1*16 -> 2*8
temp
=
add_crosstalk
(
tmap
)
temp
=
add_crosstalk
(
tmap
)
fig
=
plt
.
figure
(
figsize
=
(
20
,
60
))
fig
=
plt
.
figure
(
figsize
=
(
20
,
60
))
ax
=
plt
.
subplot
(
311
)
ax
=
plt
.
subplot
(
311
)
plt
.
imshow
(
np
.
log10
(
mapclip
.
array
+
1
),
origin
=
'lower'
,
cmap
=
'gray'
)
plt
.
imshow
(
np
.
log10
(
mapclip
.
array
+
1
),
origin
=
'lower'
,
cmap
=
'gray'
)
ax
=
plt
.
subplot
(
312
)
ax
=
plt
.
subplot
(
312
)
...
...
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