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csst-sims
csst_msc_sim
Commits
6281c265
Commit
6281c265
authored
Dec 02, 2024
by
Fang Yuedong
Browse files
add free_mem to C10_Catalog.py
parent
a3c2766c
Pipeline
#7397
failed with stage
in 0 seconds
Changes
1
Pipelines
1
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Inline
Side-by-side
catalog/C10_Catalog.py
View file @
6281c265
...
@@ -499,6 +499,10 @@ class Catalog(CatalogBase):
...
@@ -499,6 +499,10 @@ class Catalog(CatalogBase):
else
:
else
:
print
(
"number of objects in catalog: "
,
len
(
self
.
objs
))
print
(
"number of objects in catalog: "
,
len
(
self
.
objs
))
def
free_mem
(
self
,
**
kward
):
self
.
starDDL
.
freeGlobeData
()
del
self
.
starDLL
def
load_sed
(
self
,
obj
,
**
kwargs
):
def
load_sed
(
self
,
obj
,
**
kwargs
):
if
obj
.
type
==
'star'
:
if
obj
.
type
==
'star'
:
# _, wave, flux = tag_sed(
# _, wave, flux = tag_sed(
...
...
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