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Liu Dezi
csst_msc_sim
Commits
143809f7
Commit
143809f7
authored
Apr 17, 2024
by
Wei Chengliang
Browse files
update unittest
parent
d9387ab4
Changes
4
Hide whitespace changes
Inline
Side-by-side
tests/test_BF_CTE.py
View file @
143809f7
...
...
@@ -79,7 +79,8 @@ def defineFilt(chip):
class
detModule_coverage
(
unittest
.
TestCase
):
def
__init__
(
self
,
methodName
=
'runTest'
):
super
(
detModule_coverage
,
self
).
__init__
(
methodName
)
self
.
dataPath
=
"/public/home/chengliang/CSSOSDataProductsSims/csst-simulation/tests/UNIT_TEST_DATA"
##os.path.join(os.getenv('UNIT_TEST_DATA_ROOT'), 'csst_fz_gc1')
##self.dataPath = "/public/home/chengliang/CSSOSDataProductsSims/csst-simulation/tests/UNIT_TEST_DATA" ##os.path.join(os.getenv('UNIT_TEST_DATA_ROOT'), 'csst_fz_gc1')
self
.
dataPath
=
os
.
path
.
join
(
os
.
getenv
(
'UNIT_TEST_DATA_ROOT'
),
'csst_fz_msc'
)
self
.
iccd
=
1
...
...
@@ -132,11 +133,11 @@ class detModule_coverage(unittest.TestCase):
rho_trap
=
np
.
array
([
0.6
,
1.6
,
1.4
],
dtype
=
np
.
float32
)
trap_seeds
=
np
.
array
([
0
,
100
,
1000
],
dtype
=
np
.
int32
)
release_seed
=
500
image
=
fits
.
getdata
(
"UNIT_TEST_DATA/
testCTE_image_before.fits"
).
astype
(
np
.
int32
)
image
=
fits
.
getdata
(
os
.
path
.
join
(
self
.
dataPath
,
"
testCTE_image_before.fits"
)
)
.
astype
(
np
.
int32
)
#get_trap_map(trap_seeds,nx,ny,nmax,rho_trap,beta,c,".")
#bin2fits("trap.bin",".",nsp,nx,ny,nmax)
image_cti
=
CTI_sim
(
image
,
nx
,
ny
,
noverscan
,
nsp
,
nmax
,
beta
,
w
,
c
,
t
,
rho_trap
,
trap_seeds
,
release_seed
)
fits
.
writeto
(
"UNIT_TEST_DATA/
testCTE_image_after.fits"
,
data
=
image_cti
,
overwrite
=
True
)
fits
.
writeto
(
os
.
path
.
join
(
self
.
dataPath
,
"
testCTE_image_after.fits"
)
,
data
=
image_cti
,
overwrite
=
True
)
if
__name__
==
'__main__'
:
...
...
tests/test_PSFmodule.py
View file @
143809f7
...
...
@@ -39,8 +39,8 @@ def defineFilt(chip):
class
PSFInterpModule_coverage
(
unittest
.
TestCase
):
def
__init__
(
self
,
methodName
=
'runTest'
):
super
(
PSFInterpModule_coverage
,
self
).
__init__
(
methodName
)
self
.
dataPath
=
"/public/home/chengliang/CSSOSDataProductsSims/csst-simulation/tests/UNIT_TEST_DATA"
##
os.path.join(os.getenv('UNIT_TEST_DATA_ROOT'), 'csst_fz_
gc1
')
self
.
iccd
=
1
self
.
dataPath
=
os
.
path
.
join
(
os
.
getenv
(
'UNIT_TEST_DATA_ROOT'
),
'csst_fz_
msc
'
)
self
.
iccd
=
8
def
test_loadPSFSet
(
self
):
config_file
=
os
.
path
.
join
(
self
.
dataPath
,
'config_test.yaml'
)
...
...
@@ -49,7 +49,7 @@ class PSFInterpModule_coverage(unittest.TestCase):
print
(
chip
.
chipID
)
print
(
chip
.
cen_pix_x
,
chip
.
cen_pix_y
)
pathTemp
=
"/public/share/yangxuliu/CSSOSDataProductsSims/psfCube/set1_dynamic/"
pathTemp
=
self
.
dataPath
#
"/public/share/yangxuliu/CSSOSDataProductsSims/psfCube/set1_dynamic/"
psfModel
=
PSFInterp
(
chip
,
npsf
=
900
,
PSF_data_file
=
pathTemp
,
PSF_data_prefix
=
""
,
HocBuild
=
True
,
LOG_DEBUG
=
True
)
x
,
y
=
4096
,
4096
#imgPos[iobj, :] # try get the PSF at some location (1234, 1234) on the chip
...
...
tests/test_darknoise_func.py
View file @
143809f7
...
...
@@ -60,7 +60,7 @@ def defineFilt(chip):
class
detModule_coverage
(
unittest
.
TestCase
):
def
__init__
(
self
,
methodName
=
'runTest'
):
super
(
detModule_coverage
,
self
).
__init__
(
methodName
)
self
.
dataPath
=
"/public/home/chengliang/CSSOSDataProductsSims/csst-simulation/tests/UNIT_TEST_DATA"
##
os.path.join(os.getenv('UNIT_TEST_DATA_ROOT'), 'csst_fz_
gc1
')
self
.
dataPath
=
os
.
path
.
join
(
os
.
getenv
(
'UNIT_TEST_DATA_ROOT'
),
'csst_fz_
msc
'
)
self
.
iccd
=
1
def
test_add_dark
(
self
):
...
...
tests/test_prescan_overscan_func.py
View file @
143809f7
...
...
@@ -81,7 +81,7 @@ def defineFilt(chip):
class
detModule_coverage
(
unittest
.
TestCase
):
def
__init__
(
self
,
methodName
=
'runTest'
):
super
(
detModule_coverage
,
self
).
__init__
(
methodName
)
self
.
dataPath
=
"/public/home/chengliang/CSSOSDataProductsSims/csst-simulation/tests/UNIT_TEST_DATA"
##
os.path.join(os.getenv('UNIT_TEST_DATA_ROOT'), 'csst_fz_
gc1
')
self
.
dataPath
=
os
.
path
.
join
(
os
.
getenv
(
'UNIT_TEST_DATA_ROOT'
),
'csst_fz_
msc
'
)
self
.
iccd
=
1
def
test_add_prescan_overscan
(
self
):
...
...
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