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Wu Jin
CSST simulation
Commits
5fe39b53
Commit
5fe39b53
authored
Dec 17, 2021
by
Fang Yuedong
Browse files
renaming
parent
c5298bda
Changes
1
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Inline
Side-by-side
run_sim.py
View file @
5fe39b53
...
@@ -8,7 +8,7 @@ import yaml
...
@@ -8,7 +8,7 @@ import yaml
import
gc
import
gc
gc
.
enable
()
gc
.
enable
()
def
run
S
im
(
Catalog
):
def
run
_s
im
(
Catalog
):
"""
"""
Main method for simulation call.
Main method for simulation call.
"""
"""
...
@@ -59,7 +59,7 @@ def runSim(Catalog):
...
@@ -59,7 +59,7 @@ def runSim(Catalog):
chips
=
config
[
"obs_setting"
][
"run_chips"
])
chips
=
config
[
"obs_setting"
][
"run_chips"
])
if
__name__
==
'__main__'
:
if
__name__
==
'__main__'
:
run
S
im
(
Catalog
=
Catalog_example
)
run
_s
im
(
Catalog
=
Catalog_example
)
# To run cycle-3 simulation
# To run cycle-3 simulation
# from Catalog.C3Catalog import C3Catalog
# from Catalog.C3Catalog import C3Catalog
# run
S
im(Catalog=C3Catalog)
# run
_s
im(Catalog=C3Catalog)
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