Commit dcedbba4 authored by Yan Zhaojun's avatar Yan Zhaojun
Browse files

test

parent 03beac41
Pipeline #3996 passed with stage
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...@@ -11,7 +11,7 @@ Modified-History: ...@@ -11,7 +11,7 @@ Modified-History:
import unittest import unittest
import os import os
from csst_mci_sim import mci_sim from csst_mci_sim import csst_mci_sim
import sys import sys
...@@ -42,7 +42,7 @@ class TestDemoFunction(unittest.TestCase): ...@@ -42,7 +42,7 @@ class TestDemoFunction(unittest.TestCase):
sourcein = 'SCI' sourcein = 'SCI'
print(configfile) print(configfile)
mci_sim.runMCIsim(sourcein, configfile, dir_path, 1) csst_mci_sim.runMCIsim(sourcein, configfile, dir_path, 1)
self.assertEqual( self.assertEqual(
1 , 1, 1 , 1,
"case 1: SCI sim passes.", "case 1: SCI sim passes.",
......
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